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Pad definition corrected 2006.05.15, librarian@cadsoft.de CAPACITOR
IPC 2012 chip
Pad definition corrected 2006.05.15, librarian@cadsoft.de HARTING atmel (2) AVR-ISP-6 PIN HEADER
JTAG 6 Pin, 0.1" Straight avr-5-4.16 TQFP32-08 Thin Plasic Quad Flat Package Grid 0.8 mm andereBauteile 7SEG-13 7-segment DISPLAY
13 mm JUMPER SOLDER PAD
drill 1.0 mm Drill 0.032" (#67) SMD PAD
Square AVR-Projekte.de AVR-Projekte.de 3* SA52-11GWA VY 9 ZWILLING HAKA Design-Regeln fr Zwillingsleiterplatten (Stand 12.12.2008):
Diese DRU-Datei enthlt alle erforderlichen Design Einstellungen, damit Ihre Zwillingsleiterplatten bei uns fehlerfrei und kostengnstig produziert werden knnen. Die Optionen Shapes und Misc sind nicht relevant und der minimale Wert fr Roundness Shapes sollte auf 0 gesetzt werden.
bersicht der HAKA Regeln:
allgemein:
minimale Leiterbahnbreite/-abstand: 0.2 mm
Strichstrke fr Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben
kleinster Bohrdurchmesser: 0.5 mm --> kleinstes Ltauge 0.9mm
Achtung:Maximale Gre ber Alles: 100mm x 160mm (bei Einzelplatten incl. 5mm Frsabstand!!)
Restringe um DK-Bohrungen:
Aussenlagen: 0.2 mm
Polygon-Isolierungen: 0.3 mm
Achtung:
Verwenden Sie bitte nur den Vektor-Font, da nur dieser bei der Gerber-Ausgabe generiert werden kann, andere Schriftarten knnen zu Fehlern fhren!
Die Linienstrke fr Polygone sollte grer sein als 0.2mm. Es entstehen ansonsten extrem groe Datenmengen, weil Eagle die Polygone mit der angegebenen Strichstrke fllt.
Frskonturen:
werden im Dimension-Layer die Frswege mit einem 2mm Werkzeug gezeichnet, so knnen diese Daten direkt als Frsprogramm bernommen, und so die Leiterplatten kostenfrei mit jeder Kontur gefrst werden!
Der Abstand vom Kupfer zur Kontur mu mindestens 0.2mm betragen!
weitere Informationen finden Sie unter www.haka-lp.de oder bei:
HAKA Elektronik-Leiterplatten GmbH - Am Zankwald 12 - 66583 Spiesen-Elversberg - Tel.: 06821/730893
einfach bestellen unter::
www.online-Leiterplatten.de
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